1. Technical Field
The present invention is directed generally toward the testing of integrated circuit wafers. More specifically, the present invention is directed toward testing integrated circuit wafers in parallel using built-in self-test circuitry and self-marking technology.
2. Description of the Related Art
Integrated circuits (ICs) are typically manufactured in batches on a single disc of material, known as a wafer. One wafer may contain many die (the name commonly given to the individual ICs on a wafer). Environmental and other factors during the manufacturing process may and generally do cause defects in at least some of the circuits on any given wafer. An essential part of an the IC manufacturing process, then, is to detect defective ICs and discard them before they are packages for use within a circuit.
Generally, the die on a wafer are tested (xe2x80x9cprobedxe2x80x9d) by individually contacting contact pads on each die and executing a variety of functional, fault grade, automatic test pattern generation (ATPG) and parametric tests. If any of the tests fail, then the die is marked as bad. Testing then continues from die to die. For smaller devices, the test time can be acceptably short, and in some cases, the time required to mechanically move the test connection from die to die (mechanical latency) can be the most significant portion of the process. For more complex devices, the test times can be quite large.
What is needed, then, is a test technique that reduces mechanical latency and testing time.
The present invention addresses the problem of testing newly-manufactured integrated circuits at the wafer stage. Built-in self-test circuitry is used to test each of the die on a wafer in parallel. Then, when a defect is detected, the die marks itself (e.g., by physically destroying a portion of itself through burnout). The present invention eliminates the inefficiencies of serial testing of die and of mechanical latency as each die is positioned for testing.